ADVRAM

Enlighted (4156)

11-01-2009, 17:05

Hello,all.

I'm interested to find the hw circuitry schemas of ADVRAM.
Most of us, in memory contented architecture are concerned about wait states to the cpu while accessing vram if there is a video hw access in progress. But my question is:
Can a in progress z80 memory access, in somewhat give a delay to video hw? Surely no. but how is guaranteed on ADVRAM that the z80 memory read/write cycle does not interfere with video access?

By flyguille

Prophet (3031)

11-01-2009, 18:46

ADVRAM has two buses of everything, two devices can to access it without interfere.

By flyguille

Prophet (3031)

11-01-2009, 18:51

ja, just tried ADVRAM % GOOGLE, and what was the first page found

http://www.700km.com.br/mundobizarro/advram/

somebody declared its inventions AS STANDARD without consulting nobody... jajajajajaajaj

By Fudeba

Expert (113)

11-01-2009, 19:12

Well, despite the fact the hardware never was really produced, a "standard" can be defined by anyone. It was never said it was an *official* MSX standard.
The standard defines that if you want to call a device "ADVRAM", then it should meet those specifications. That's all.
Anyway, ADVRAM was extensively discussed on the community (at least in Brazillian community) and that page was not written by ADVRAM "inventor", but by someone that discussed its specifications and implemented it on his emulator (BrMSX).

Take a look in the bottom of that page:
----
The ADVRAM original idea was told to me by Márcio of the Other Side MSX Club, during the ExpoSALT 2000 meeting.
I liked the idea and told it to Ademir Carchano, who implemented the first hardware prototype in only four months.
Many thanks to the people who contributed to the standard including Daniel Caetano, Werner Kai, Leonard Oliveira, and the people from the #msxzone IRC channel.
----

And no, ADVRAM has not two buses, AFAIK. Z80 should access the VRAM while the VDP is not using it (between consecutive accesses). This require an extremely tight timing and sometimes the Z80 could be put in WAIT state, causing an effect timilar to ZX Spectrum contended memory use.

By PingPong

Enlighted (4156)

11-01-2009, 19:26

Fudeba, are you sure of what are you saying?
If the z80 can access only when the VDP is not using vram, then the results of the benchmarks will not be possible. the main factor of slowness is the limited bandwidth of vdp, and even with fast vram chips the vdp is the bottleneck.
even on traditional msx vdp's the main limiting factor is not the i/o port based access, instead the delay one must write between two accesses. If the vdp owns continusly the vram, (giving a slot between 8us) what chances had the z80 to access it quickly?
an ld (hl),a works almost fast as out (c),a ....

By PingPong

Enlighted (4156)

11-01-2009, 19:31

And If the z80 access is too slow and takes the bus too much locking the vdp ? (that cannot be locked) What happens?

By flyguille

Prophet (3031)

11-01-2009, 20:05

I was thinking on dual bus RAM chips, and not in that article/invention. Just now I don't remember its family-name.

By Manuel

Ascended (19691)

12-01-2009, 09:20

Note that ADVRAM is emulated also by openMSX, maybe that helps when trying it out a bit. arnoldm knows the details on how accurate it is.

By Fudeba

Expert (113)

12-01-2009, 16:32

PingPong: Well, I am almost sure, no dualport RAM was planned on ADVRAM ("that would be too expensive and too easy" was the reason given by Ademir). The limited speed enhancement was one of the consequences (note the limited success of 3.57MHz benchmarks). These results are based on Ademir circuit simulations and Ricardo Bittencourt's knowledge on VDP and CPU timings.
The performance would be a lot better with faster CPUs (R800, or eZ80 @ 50MHz... or even Z38x @18MHz), since they would be able to do more on VRAM on the tight time-gaps were VDP is not using VRAM. However, Ademir was able to sync everything up to 7MHz Z80 only. No luck when the CPU was running @10MHz or more (I don't know the real reason. AFAIR, the circuit worked on simulation, using a fast ALTERA, but I believe Ademir hadn't the required equipment - like a really fast oscilloscope - to adjust the real hardware on higher speeds). Since Ademir planned this hardware for UNI computers (which would run at higher frequencies), these problems kind of killed both ADVRAM and UNI.
Note: this is NOT an official statement or information. This is just a composition of loose comments I'd heard along the past 5 years.

By arnold_m

Master (173)

12-01-2009, 18:30

OpenMSX emulates ADVRAM as if dual-ported RAM is used; no delays are introduced by the VDP also accessing the vram.
To do better we would need to have cycle accurate timings of the VDP read and write actions.

By Fudeba

Expert (113)

13-01-2009, 19:04

I forgot to answer... The Z80 access is delayed (wait states generated as needed) until there is a time window to access the VRAM.

And If the z80 access is too slow and takes the bus too much locking the vdp ? (that cannot be locked) What happens?

I believe this will never happen, given a faster enough Z80. Remember Z80 takes about 1 or 2 cycles of VRAM access.
Anyway, if it happens, VDP will read pull-up data, since ADVRAM is(*), in fact, a big bus switch activated on specific Z80 and VDP signal configurations. It doesn't work like ZX Spectrum (where both ULA and Z80 are attached to the bus at the same time).

(*) As designed.