Philips NMS 8255/8250 memory upgrade (again!)

IC111, I would guess that's the one, that is meant in the 512K instructions also. The 256K instructions mention it, and it's the closest 32 on the board anyway.

I'm thinking SRAM also, much easier I would guess. The downside is, if a rom game is loaded in the ram, it stays in SRAM a few seconds after poweroff, so changing game takes little longer...

Hi zPasi and RetroTechie, thanks for your replies!

That's my guess, too (note: I was wondering above why the 256kb is connecting a different pin of the added 74ls139 than the 512kb upgrade - probably because less addressing is needed).

The problem here is I do not want to guess - I want to be sure before I start soldering, since if the thing is not built properly in the first place, it will be impossible for me to troubleshoot. I want to be in the stage, where troubleshooting = re-checking all connections with multimeter.

Also I do not think soldering by guessing is the right approach, since there is bound to be people here who have already built this upgrade, and those who understand memory mappers properly .

Currently, I'm reading the memory mapper documentations from Hans Ottens site, and also the 8250/55 service manual, and trying to understand what I am actually doing here.

I can see the rationale here. There's just the problem of lack of ready-made instructions - this is why I ordered the 4464 chips since there are some instructions available for using them. Using a more modern chip, might be simpler for someone adept with electronics, which I am not.

I should note here, that I do not work with electronics or anything of the kind for my daytime job. This is just a hobby for me (one of many, and I do other things than electronics in my free time!). In practice, when I see things like "STROBE signal" I go to Wikipedia and try to figure out what the h*** does it mean .

So I agree with you, but when you start to talk about 4x4M chips, I have only a vague idea about what you mean, so it is still way over my head do just start building it.

That being said, maybe with the help of this forum, a building guide for dummies (i.e. buy these parts, connect that pin to here and that one here) for memory expansion with newer chips could be made?

Also, no-one (aside for zPasis guesswork) has jet answered the original question: what is the STROBE signal? It must be called something else in SM? If zPasi is right, according to the SM, the STROBE is actually CAS2/E - and I believe that may actually make sense, since I think I've seen that in S3527 SM for the RAM slot selection - need to check that document, too. So the 74LS39 does RAM page(?) selection with the help of the 670, if CAS2/E is high? (This is probably clear as peaches for someone, but not for me )

Hmm,

I'm really starting to suspect that the 512kb instruction has a small but detrimental error in the schematic! Can someone who has build this (or has definite knowledge about the memory mapper) confirm this? It is certainly possible I've misunderstood something! Also, some of the documentation I've been reading is in Dutch (or some other language)

The error: I believe STROBE is indeed CAS2/E and should be connected to pins 1,15 of 74ls139, and pins 2 & 14 should be connected to pin 9 of the added 670 - and consequently 125 pin 5 (in the schematic these are swapped!). According to 139 datasheet, pin 1 is E1 and pin15 E2. It makes no sense to connect CAS2/E anywhere else? This would be in line with other memory mapper instructions I can find, and also the circuit just makes more sense to me this way...

Cheers!

The problem here is the vagueness of the 512kb instruction; if it was only the STROBE / CAS2/E vagueness, but there's also the difference in where it is connected to: pin1 (in 256kb expansion and some others) vs. 512kb expansion (pin2 = 1A_0, address input). I believe there's an error in the latter at the moment (see my previous post), but since this is not my cup of tea, I'd like someone to confirm (or tell me I'm wrong and that the current schematic is right).

(Also, I believe it needs one page line more (=double the amount of 16kb pages) - no more address lines?)

EDIT: Also, the error I've described is something easy to slip by - if there indeed is an error. Depending on the software used to draw the schematic, it could just be made with a single unintentional "click+drag" of 3mm, since it's actually just one connection in the schematic... and an experts brain may "fix" this error when he/she sees it and go unnoticed...

Yes, but we can't be sure. He might have never read your post (though unlikely since there was several hours between your posts) - or maybe he just wanted to promote using newer, better chips

I've been precisely trying to do what you say. But this is not my cup of tea. And someone / something has been constantly interrupting me today

I think I will wait for more comments. There's bound to be someone who knows. Of course, I could just test which way the LS139 should be wired up, and which way it works, but I believe it is better wait for some answers than to try based on guesswork.

Also, I've already designed my workflow so that I can easily revert the changes. There's several reasons for it: I'm definitely not sure about the 4464 I've bought, so it is nice to be able to return using the original chips - or make an upgrade with some SRAM, provided I can find / gather enough information / knowledge to put together clear enough schematics for me to follow =)

(oh - post#100 #102! )

There's nothing inside a crystal to leak... at most it would be air leaking IN! Probably just some corrosion on that exposed copper pad, or glue remains? Either way: ignore.

For hardware builders/modders, that's the only correct approach: understand first, THEN build. Not follow some dumb list of "cut here, connect that, ..." etc. If you don't know how [what you're building] works, then you can't fix it in case of problems. If you do understand how it works, then it is -relatively- easy to fix / work around problems, swap some pins, extend circuit a bit further, etc.

As for MSX memory mappers (RAM), the first thing you'll need is "expanded address lines" (usually named MA14, MA15, ..., shown as EA14/15 in the NMS8250/55 service manual). When addressing memory, A0..A13 determine which location inside a 16 KB block. For non-mapper RAM, A14 and A15 then determine which 16 KB block within the Z80's 64K address space.

But with a memory mapper, A14 and A15 are used as 'selectors', which choose a register (of which there are 4), whose contents decides which 16KB block within the mapper is addressed. Contents of these "mapper registers" is what the programmer wrote (and STUPID programmers also read) to I/O ports FC..FFh. This re-directing of memory blocks is called "mapping", thus the name memory mapper.

It gets more complicated: quite a few crappy software exists that also reads these registers. To keep that software working, read-back of the registers is provided. Note that this is NOT an absolute 'must' ! A mapper where the registers can only be written but not read, should still be considered a properly working mapper. It's just that some (crappy) software has problems with that.

Now when the I/O registers are written (or read), A0 and A1 decide which of the 4 registers. But when mapper RAM is accessed, it's A14/A15 that decide which register. Therefore in most mappers, a 'selector' is used that switches between A0/A1 and A14/A15. In the NMS8250/55, this is IC150 (74LS157).

The registers themselves (always 4 values) usually come in the form of 74LS670 or 74HC(T)670 IC's. In the NMS8250/55, that's IC149. How many, depends on the WIDTH of the registers, this depends on the # of mapper blocks, which depends on the mapper size:
64KB = 4 blocks = 2-bit block # = D0/D1 -> MA14/MA15
128KB = 8 blocks = 3-bit block # = D0..D2 -> MA14..MA16
256KB = 16 blocks = 4-bit block # = D0..D3 -> MA14..MA17
512KB = 32 blocks = 5-bit block # = D0..D4 -> MA14..MA18
1024KB = 64 blocks = 6-bit block # = D0..D5 -> MA14..MA19
2048KB = 128 blocks = 7-bit block # = D0..D6 -> MA14..MA20
4096KB = 256 blocks = 8-bit block # = D0..D7 -> MA14..MA21

In a factory-state NMS8250/55, there's a 128K mapper, and that's why you see D0/D1/D2 connected to IC149, it keeps 3 bits (to choose from 8 mapper blocks) for each of the 4 mapper registers. Btw: dunno why IC131 (pin 11/12) is used to buffer D0 there, looks kinda pointless...

When the mapper I/O ports are read, the other gates in IC131 (74LS125) are used to put the register bits back onto the data bus.

So to expand the mapper registers (width), the easiest way is to piggy-back a 74HCT670 on top of IC149. With all pins 1:1 connected, except the data in- and outputs. Then you wire up D3 and D4 (for 512KB) and D5 too (for 1 MB) to the inputs. Corresponding outputs are your expanded address lines MA17/18 (and /19 in case of 1 MB).

To also have read-back for those extra bits, you could put a 74HCT125 on top of IC131, and wire up the extra address + data lines the same way as is done for D0..D2.

With a 512K*8 bit SRAM, you're basically done then. Beside Vcc/GND, address line go to the SRAM's A.. inputs (in any order!), data lines to the SRAM's I/O pins (also in any order). Pick a free (internal) /SLTSL signal, in this case I'd go for /SLT31 (from S3527 pin 28), and wire to the SRAM's /CE input. Z80's /RD goes to /OE input, /WR goes to /WE input. Done. As said, re-purposing a ROM socket to make most SRAM connections would be easiest.

With 2 of those SRAMs (for 1 MB), you'd have one more MA.. line left over, and you use that with a 74HCT139 to 'split' that /SLTSL signal into 2 /CE signals (one for each chip). So /SLT31 to a /G input of the '139 (pin 1 or 15), the expanded address line to corresponding "A" or "B" input (doesn't matter - just pick one), the other of those 2 to Vcc or GND (again: doesn't matter which), and then check "Function Table" in the datasheet to see which Y.. pins to use as /CE for the SRAMs.

Indeed it looks like that 1st mentioned circuit has a mistake in it. But know that decoders like the '139 can often be (ab)used in different ways to achieve the same goal. So what looks like a mistake can be just a different way to obtain the required signals (I'm too lazy to check). Maybe it was done some time to swap some pins & make pcb layout easier, and others just copied that. Who knows.

With DRAMs, all those address line go into multiplexers (IC146/147) and you get "multiplexed address lines" (L0..L7 in the service manual). Basically each of those is two A.. lines in one ("MUX" signal indicates which). Then you have to deal with DRAM refresh. Control signal timing is also much more complicated than for SRAMs.

But don't stare yourself blind on all those mapper circuits! There's many ways that lead to Rome. For example in a 512 KB mapper of my own, I used a programmable logic device (CPLD) to do all that decode-I/O-ports-'670-register stuff. Looks very different, but operation principles & end result is the same.

"Strobe" is a generic name for a signal that goes "active" for a short while when something happens. What exactly it means, depends on context.

In this case, context is those Column Address Strobe inputs (pin 16) of the DRAMs (IC133..IC136). The NMS8250/55 uses EA16 (IC149 pin 7), two OR gates and an inverter (IC111/IC121) to split /CAS2/E signal into /CAS1 and /CAS2.
A decoder like the '139 can do the same. So yes, /CAS2/E signal is that "strobe" you'd put into /G input of that '139. And then Y.. outputs are the "strobes" that come out...