Sources for a CPLD implementation of a SCC chip are to found here (ESE factory): scc vhdl
My goals is to replace an existing SCC with one in a CPLD (don't ask why).
I would prefer a Cyclone II (but for this purpose I think it's a bit overkill).
Are the source files given enough to complete this task with Quartus II?
When I compiled it it said it uses 26 pins of the CPLD. But the SCC has 48 pins.
The also give the instructions to rename ram.vhd → std_ram.vhd and lpm_ram.vhd → ram.vhd en compileer.
There is also a .acf file included for the second 'non-cpld' system.
Hi Gregory
Yes these files work great with a EP2C5.
Normaly when you compile, the project needs 45 pins but lot of them can be removed.
ACF file is not needed.
Flow Status Successful - Wed Jun 23 21:03:01 2021
Quartus II 64-Bit Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
Revision Name scc
Top-level Entity Name scc
Family Cyclone IV E
Device EP4CE6E22C8
Timing Models Final
Total logic elements 708 / 6,272 ( 11 % )
Total combinational functions 644 / 6,272 ( 10 % )
Dedicated logic registers 241 / 6,272 ( 4 % )
Total registers 241
Total pins 45 / 92 ( 49 % )
Total virtual pins 0
Total memory bits 2,048 / 276,480 ( < 1 % )
Embedded Multiplier 9-bit elements 0 / 30 ( 0 % )
Total PLLs 0 / 2 ( 0 % )
Thanks Fabf for the response, I'll give it a try.
Did you have to change the names of the sourcefiles ram.vhd and lpm_ram.vhd?
So no possibility of running it on a cyclone II (cause I have a lot of them lying around)?
This works well with cyclone II but not with CPLD cause of 2KB internal RAM.
I rename ram.vhd and lpm_ram.vhd but not shure it's needed.
I don't understand why you have only 26pins ?
Hi Gregory
Yes these files work great with a EP2C5.
Normaly when you compile, the project needs 45 pins but lot of them can be removed.
ACF file is not needed.
Flow Status Successful - Wed Jun 23 21:03:01 2021
Quartus II 64-Bit Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
Revision Name scc
Top-level Entity Name scc
Family Cyclone IV E
Device EP4CE6E22C8
Timing Models Final
Total logic elements 708 / 6,272 ( 11 % )
Total combinational functions 644 / 6,272 ( 10 % )
Dedicated logic registers 241 / 6,272 ( 4 % )
Total registers 241
Total pins 45 / 92 ( 49 % )
Total virtual pins 0
Total memory bits 2,048 / 276,480 ( < 1 % )
Embedded Multiplier 9-bit elements 0 / 30 ( 0 % )
Total PLLs 0 / 2 ( 0 % )
I got problem when trying to run the ram files, it gives me the library doesn't have lpm and ram too. I am not sure if these file can replace the whole konami chip because I don't see mapper outputs (MA13 - MA 18) depending on the size. So, I am assuming you can find the mapper from somewhere and only use these files to generate the SCC sound. Having said that, does chip select signal have to be fed to to the FPGA to have the SCC sound at the end?
I counted about 36 - 38 input and output (equivalent to pins) from that those files excluding the ram ones.
Does anyone if the SCC project can be implement on Xilinix XC9536?
